1. Field
This disclosure relates generally to semiconductors, and more specifically, to pipelined memory circuits.
2. Related Art
Various memory circuits are implemented in pipelined stages that are a sequence of functional stages for performing specific functions in several steps. While information is internally processed in a serial fashion, all stages work concurrently to give a higher throughput than if all the steps are completed before starting a next task. Pipelined stages are typically clocked in a synchronous manner wherein a single clock signal controls all the stages. Every stage must therefore complete its work within at least one or more clock periods.
Traditional pipelined memory architectures are often designed to have equally timed stages. As a result, the clock cycle time within a pipelined structure typically differs from a system clock within which the memory functions. Such differences typically result in timing inefficiencies which can result in increased access time.
In order to improve power consumption and speed, asynchronous pipelines have been proposed where all stages proceed independently and do not switch at the same time. Control mechanisms must be used to maintain every pair of adjacent stages in synchronization. The implementation of these control mechanisms is complex and additional circuitry is often required to synchronize the communication of input and output information with external circuitry.